LED with substrate modifications for enhanced light extraction and method of making same

ABSTRACT

The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw blade or a masked etching technique. Sidewall cuts may also be made in the emitting surface prior to the RIE process. A light absorbing damaged layer of material associated with saw cutting is removed by the RIE process. The surface morphology created by the RIE process may be emulated using different, various combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

RELATED APPLICATION DATA

This application claims the benefit of U.S. Provisional patentapplication Ser. No. 60/585,326 filed Jul. 2, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to light emitting diodes (LEDs) and moreparticularly to new surface morphologies for enhancing the extraction oflight from LEDs and methods of manufacturing LEDs having such surfaces.

2. Description of Related Art

Light emitting diodes (LEDs) are an important class of solid statedevices that convert electric energy to light and generally comprise anactive layer of semiconductor material sandwiched between two oppositelydoped layers. When a bias is applied across the doped layers, holes andelectrons are injected into the active layer where they recombine togenerate light. Light is emitted omnidirectionally from the active layerand from all surfaces of the LED.

There has been a great deal of recent interest in LEDs formed ofGroup-III nitride based material systems because of their uniquecombination of material characteristics including high breakdown fields,wide bandgaps (3.36 eV for GaN at room temperature), large conductionband offset, and high saturated electron drift velocity. The doped andactive layers are typically formed on a substrate that can be made ofdifferent materials such as silicon (Si), silicon carbide (SiC), andsapphire (Al₂O₃). SiC wafers are often preferred because they have amuch closer crystal lattice match to Group-III nitrides, which resultsin Group III nitride films of higher quality. SiC also has a very highthermal conductivity so that the total output power of Group III nitridedevices on SiC is not limited by the thermal resistance of the wafer (asis the case with some devices formed on sapphire or Si). Also, theavailability of semi insulating SiC wafers provides the capacity fordevice isolation and reduced parasitic capacitance that make commercialdevices possible. SiC substrates are available from Cree, Inc., ofDurham, N.C. and methods for producing them are set forth in thescientific literature as well as in U.S. Patents, Nos. Re. 34,861;4,946,547; and 5,200,022.

The efficient extraction of light from LEDs is a major concern in thefabrication of high efficiency LEDs. For conventional LEDs with a singleout-coupling surface, the external quantum efficiency is limited bytotal internal reflection (TIR) of light from the LED's emission regionthat passes through the substrate. TIR can be caused by the largedifference in the refractive index between the LED's semiconductor andsurrounding ambient. LEDs with SiC substrates have relatively low lightextraction efficiencies because the high index of refraction of SiC(approximately 2.7) compared to the index of refraction for thesurrounding material, such as epoxy (approximately 1.5). This differenceresults in a small escape cone from which light rays from the activearea can transmit from the SiC substrate into the epoxy and ultimatelyescape from the LED package.

Different approaches have been developed to reduce TIR and improveoverall light extraction, with one of the more popular being surfacetexturing. Surface texturing increases the light's escape probability byproviding a varying surface that allows photons multiple opportunitiesto find an escape cone. Light that does not find an escape conecontinues to experience TIR, and reflects off the textured surface atdifferent angles until it finds an escape cone. The benefits of surfacetexturing have been discussed in several articles. [See Windisch et al.,Impact of Texture-Enhanced Transmission on High-Efficiency SurfaceTextured Light Emitting Diodes, Appl. Phys. Lett., Vol. 79, No. 15,October 2001, Pgs. 2316-2317; Schnitzer et al. 30% External QuantumEfficiency From Surface Textured, Thin Film Light Emitting Diodes, Appl.Phys. Lett., Vol 64, No. 16, October 1993, Pgs. 2174-2176; Windisch etal. Light Extraction Mechanisms in High-Efficiency Surface TexturedLight Emitting Diodes, IEEE Journal on Selected Topics in QuantumElectronics, Vol. 8, No. 2, March/April 2002, Pgs. 248-255; Streubel etal. High Brightness AlGaNInP Light Emitting Diodes, IEEE Journal onSelected Topics in Quantum Electronics, Vol. 8, No. March/April 2002].

U.S. Pat. No. 6,410,942, assigned to Cree, Inc., discloses an LEDstructure that includes an array of electrically interconnected microLEDs formed between first and second spreading layers. When a bias isapplied across the spreaders, the micro LEDs emit light. Light from eachof the micro LEDs reaches a surface after traveling only a shortdistance, thereby reducing TIR.

U.S. Pat. No. 6,657,236, also assigned to Cree Inc., disclosesstructures for enhancing light extraction in LEDs through the use ofinternal and external optical elements formed in an array. The opticalelements have many different shapes, such as hemispheres and pyramids,and may be located on the surface of, or within, various layers of theLED. The elements provide surfaces from which light refracts orscatters.

SUMMARY OF THE INVENTION

Briefly, and in general terms, the invention is directed to lightemitting diodes (LEDs) formed by processes that allow for the creationof surfaces that provide enhanced light extraction and methods ofmanufacturing LEDs having such surfaces. In one of several aspects, theinvention relates to a method of fabricating an LED that includes asubstrate having a light emitting surface. The method includes applyinga reactive ion etch (RIE) process to at least a portion of the lightemitting surface for a time duration sufficient to change the morphologyof the surface.

In another aspect, the invention relates to a method of fabricating anLED including a substrate having a light emitting surface having atleast one cut surface with a light absorbing damaged layer of material.The method includes applying a reactive ion etch (RIE) process to thecut surface to remove at least a portion of the damaged layer ofmaterial.

In another aspect, the invention relates to an LED formed by a processthat includes growing a light emission region on a first-side surface ofa substrate. The light emission region includes a p-type layer ofmaterial, an n-type layer of material and an active layer between thep-type layer and the n-type layer. The process also includes applying aRIE process to at least a portion of the second-side surface of thesubstrate opposite the first-side surface for a time duration sufficientto change the morphology of the surface.

In yet another aspect, the invention relates to an LED formed by aprocess that includes growing a light emission region on a first-sidesurface of a substrate. The light emission region includes a p-typelayer of material, an n-type layer of material and an active layerbetween the p-type layer and the n-type layer. The process also includescreating cuts in a second-side surface of the substrate opposite thefirst-side surface to form at least one cut surface having a lightabsorbing damaged layer of material. The process further includesapplying a RIE process to at least a portion of the cut surface for atime duration sufficient to remove at least a portion of the surfacedamage.

In another aspect the invention relates to a light emitting diode (LED)that includes a substrate having a light emitting surface having an RIEetched surface with a dimpled texture. The LED also includes a lightemission region on a surface of the substrate. The light emission regionincludes an active layer between first and second oppositely dopedlayers.

In yet another aspect, the invention relates to a light emitting diode(LED) that includes a conductive substrate having a first surface and asecond surface. A portion of the first surface has a moth-eyemorphology. The LED also includes a light emission region on the secondsurface. The light emission region includes an active layer betweenfirst and second oppositely doped layers. The LED further includes afirst contact on the first surface that is in contact with one of thefirst or second doped layers and a second contact in contact with theother of the first or second doped layers.

In still another aspect, the invention involves a method of fabricatinga light emitting diode (LED) that includes growing a light emissionregion on a first surface of a substrate. The light emission regionincludes an active layer between first and second oppositely dopedlayers. The method also includes creating a moth-eye morphology in atleast a portion of a second surface of the substrate, forming a firstcontact on the second surface of the substrate that is in contact withone of the first or second doped layers, and forming a second contact incontact with the other of the first or second doped layers.

In another aspect, the invention relates to another method offabricating a light emitting diode (LED). This method includes growing alight emission region on a first surface of a substrate. The lightemission region includes an active layer between first and secondoppositely doped layers. The method also includes forming a layer on asecond surface of the substrate. This layer has a refractive indexsubstantially the same as the substrate and a moth-eye surfacemorphology. The method further includes forming a first contact on thelayer and in contact with one of the first or second doped layers andforming a second contact in contact with the other of the first orsecond doped layers.

These and other aspects and advantages of the invention will becomeapparent from the following detailed description and the accompanyingdrawings which illustrate by way of example the features of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of an LED including an emitting surfacehaving a modified surface morphology;

FIG. 2 is a sectional view of an LED including an emitting surface withetched features;

FIG. 3 is a sectional view of an LED including an emitting surfacehaving etched features and sidewall cuts;

FIG. 4 is an image of an uncut surface having a dimpled surfacemorphology resulting from an ICP-RIE process;

FIG. 5 is an image of the bottom of a bevel cut surface following anICP-RIE process;

FIG. 6 is a 20 μm×20 μm scale rendering of a substrate surface prior tobeing modified;

FIG. 7 is a 100 μm×100 μm scale rending of a substrate surface afterICP-RIE etching for a first time duration;

FIG. 8 is a 20 μm×20 μm scale rending of a substrate surface afterICP-RIE etching for a second time duration greater than the timeduration of FIG. 7;

FIG. 9 is optical microscope images showing surface morphologyevolution;

FIG. 10 is a graph of data for several wafers showing average substratethickness removed as a function of etch time;

FIG. 11 is a graph of total integrated scatter signal from 4H-SiC wafersas a function of etch time;

FIGS. 12-18 are photographs of examples of various bevel cuts;

FIG. 19 is a sectional view of an LED including an emitting surfacehaving a moth-eye surface morphology;

FIG. 20 is a top view of the of the LED of FIG. 15;

FIG. 21 is a sectional view of an LED including a moth-eye emittingsurface with an overlying layer of transparent conducting material;

FIG. 22 is a sectional view of an LED including a moth-eye emittingsurface formed in a current spreading region of the substrate;

FIG. 23 is a sectional image of a moth-eye surface;

FIG. 24 is a sectional view of an LED substrate having a non-continuouslayer formed on its top surface; and

FIG. 25 is a sectional view of an LED including an additional,moth-eye-surfaced layer on its substrate.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides improved light extraction for lightemitting diodes (LEDs) through the addition of a particular type ofsurface morphology to the back surface of the LED substrate. The surfacemorphology is created in the substrate through one or more additionalsteps in the LED fabrication process.

In one embodiment the back surface morphology of a SiC substrate ismodified using a reactive ion etch (RIE) process and more particularlyan inductively coupled plasma reactive ion etch (ICP-RIE) process. Thisprocess creates one or more surface areas characterized by a dimpledtexture on a microscopic scale. The dimpled surface provides a varyingsurface that allows light that would otherwise be trapped in the LED, bytotal internal reflection (TIR), to escape from the substrate tocontribute to light emission. The variations in the surface increase thechances that the TIR light will reach the substrate surface within thecritical angle and will be emitted. For light that does not escape thesubstrate through the surface, the variations of the surface reflect thelight at different angles, increasing the chances that the light willescape on the next pass. The resultant scattering surface morphologyleads to an improvement in light extraction and more light out of apackaged LED die compared to a conventional device.

In another embodiment, etched features, such as pyramids or truncatedpyramids, are created in the substrate surface prior to the RIE process.These etched features are created by cutting macroscopic facets orbevels into the SiC using an angled saw blade. Despite optical modelingresults suggesting they should, the bevel cuts do not by themselvesresult in improved light output. This is because the process of cuttingthe SiC substrate is believed to leave an absorbing damaged layer ofmaterial at the cut surfaces. In this instance, the RIE process removesthe damaged layer of material at the cut surfaces and creates a dimpledsurface on one or more substrate surface areas. The combination of thescattering dimpled surface morphology and the removal of damagedmaterial left by the substrate cutting provides improved light outputrelative to a conventional device.

In another embodiment of the invention, etched features, such aspyramids, truncated pyramids, cones, hexagonal pyramids, etc., arecreated in the substrate surface using known masking techniques incombination with SiC etching processes, including the RIE process andwet chemistry processes such as GaP etching. These etched features maybe made smaller, in both height and surface area, to produce a substratesurface having a more dense concentration of etched features than asurface with etched features made using the cutting technique. Inanother embodiment, the RIE process is applied to the substrate backsurface after etched features have been created in the SiC and afterconventional sidewall cuts have been made.

Referring now to the drawings and particularly to FIG. 1, there is shownone embodiment of an LED package 10 according to the present invention,which includes an LED 12 comprising a substrate 14 having a modifiedback surface 16 to improve light extraction of LED light passing throughthe substrate. The substrate 14 can be made of many materials and can bemany different thicknesses, with a suitable substrate being a 4Hpolytype of silicon carbide with a thickness range of 125-500 microns,although other silicon carbide polytypes can also be used including 3C,6H and 15R polytypes. Silicon carbide has a much closer crystal latticematch to Group III nitrides than sapphire and results in Group IIInitride films of higher quality. Silicon carbide also has a very highthermal conductivity so that the total output power of Group III nitridedevices on silicon carbide is not limited by the thermal dissipation ofthe substrate (as may be the case with some devices formed on sapphire).Also, the availability of silicon carbide substrates provides thecapacity for device isolation and reduced parasitic capacitance thatmake commercial devices possible.

The LED 12 comprises a standard emission region 18 formed on thesubstrate 14 using known processes such as metal-organic chemical vapordeposition (MOCVD). The operational details of conventional LEDs areknown and are only briefly discussed. The LED's emission region 18 caninclude an active layer sandwiched between two oppositely doped layers,with the layers having standard thicknesses and the active layeremitting light omnidirectionally when a bias is applied across theoppositely doped layers.

The layers of the emission region may be fabricated from differentmaterial systems such as the Group III nitride based material systems.Group III nitrides refer to those semiconductor compounds formed betweennitrogen and the elements in the Group III of the periodic table,usually aluminum (Al), gallium (Ga), and indium (In). The term alsorefers to ternary and tertiary compounds such as AlGaN and AlInGaN. In apreferred embodiment, the material forming the doped layers is GaN andthe material forming the active layer is InGaN. In alternativeembodiments the material of the doped layers may be AlGaN, AlGaAs orAlGaInP.

The LED 12 is arranged in the package 10 in a flip-chip orientation withthe top of the substrate 14 being the LED's primary emission surface.Other surfaces of the substrate 14, such as the sides, also emit lightbut the top surface is generally the primary emission surface. The LED12 is flip-chip mounted on first and second metal layers or solder bumps20 a, 20 b which are part of a submount 22. A first contact 24 iscoupled between the first metal layer 20 a and one of the oppositelydoped layers in the emission region 18 and a second contact 26 iscoupled between the second metal layer 20 b and the emission region'sother doped layer. A bias can be applied to the contacts 24, 26 throughthe first and second metal layers 20 a, 20 b, and the bias is thenconducted through the contact 24, 26 to the oppositely doped layers inthe emission region, causing the active layer to emit light.

In other LED embodiments having a substrate that is conductive enough totransmit a charge, a substrate contact 28 can be used to apply a bias toone of the oppositely doped layers. The other doped layer is contactedto one of the contacts 24, 26 arranged between the metal layers 20 a, 20b and the LED. A bias is applied to the LED through contact 28 and oneof the metal layers 20 a, 20 b, and the bias can be conducted to thesubstrate contact from the other of the metal layers, through aconductive wire (not shown) that runs from the metal layer to thesubstrate contact.

The top surface of the metal layers 20 a, 20 b can also be reflective sothat light emitted from the emission region toward the metal layers isreflected back to contribute to the overall emission of the LED package10. The LED 12 and its contacts can be encased in a clear protectivematerial 30, which is typically a transparent epoxy covering the LED 12and the top surface of the metal layers 20 a, 20 b.

Alternatively, the LED 12 can be mounted on the horizontal base of a“metal cup” that typically has conductive paths (not shown) for applyinga bias across the contacts on the emission regions oppositely dopedlayers. The top surface of the metal cup can also be reflective toreflect light from the emission region such that the light contributesto the light emission of the LED package.

The substrate 14 comprises a modified back surface 16 that, in theflip-chip arrangement of the LED 12 is the top and primary emissionsurface of the LED. The modified surface 16 enhances the light emissionof the LED 12. The efficiency of conventional LEDs is limited by theirinability to emit all of the light that is generated by the activelayer. When the flip-chip arranged LED is emitting, light reaches theprimary emitting substrate surface at many different angles. Typicalsubstrate semiconductor materials have a high index of refractioncompared to ambient air or encapsulating epoxy. Light traveling from aregion having a high index of refraction to a region with a low index ofrefraction that is within a certain critical angle (relative to thesurface normal direction) will cross to the lower index region. Lightthat reaches the surface beyond the critical angle will not cross butwill experience total internal reflection (TIR). In the case of an LED,the TIR light can continue to be reflected within the LED until it isabsorbed. Because of this phenomenon, much of the light generated byconventional LEDs does not emit, degrading its efficiency.

The modified surface 16 improves light extraction of the LED 12 byproviding a varying surface that allows light that would otherwise betrapped in the LED, by total internal reflection (TIR), to escape fromthe substrate to contribute to light emission. The variations in themodified surface increase the chances that the TIR light will reach thesubstrate surface within the critical angle and will be emitted. Forlight that does not escape the substrate through the modified surface,the variations of the modified surface reflect the light at differentangles, increasing the chances that the light will escape on the nextpass.

Details on the characteristics of the modified surface and the processof creating the modified surface are provided below, within the contextof various exemplary process runs. However, prior to describing theseprocess runs, additional embodiments of LEDs having a modified substratesurface are described.

Many different types of LEDs can utilize a modified surface according tothe present invention to increase light extraction. FIG. 2 shows anotherembodiment of an LED package 40 according to the present invention thatincludes an LED 42 having a substrate 44 with a semiconductor emissionregion 46 formed on one of its surfaces. The emission region 46 issimilar to the emission region 18 in FIG. 1. The LED 42 is mounted onfirst and second metal layers 48 a, 48 b having contacts 50, 52 tocontact the oppositely doped layers in the emission region 46. A biasapplied to the metal layers 48 a, 48 b can be applied to the oppositelydoped layers through the contacts 50, 52. The LED 42 is flip-chipmounted such that the substrate's bottom surface is the primary emittingsurface of the LED 42. The LED 42 can also be encased in a protectivetransparent epoxy 54.

The emitting surface 56 of the LED (surface of substrate 44) is notflat, but instead has a plurality of etched features 57, which in theconfiguration of FIG. 2, are truncated pyramids. The truncated pyramids57 may be formed by cutting a plurality of bevel cuts 58 in a gridpattern using an angled saw blade. The size and shape of the truncatedpyramids 57 may be varied by adjusting the depth to which the saw bladecuts into the surface of the substrate 44. In another configuration, thecut depth may be set so as to form a pyramid. It is known that thecutting process produces substantially smooth cut surfaces 59 having anoverlying layer of damaged material that is light absorbing.

Upon formation of the etched features 57, the ICP-RIE process is appliedto the emitting surface 56, including the cut surfaces 59 and the uncutsurfaces 60. The end result is an emitting surface 56 having numerousdimpled surface areas corresponding to the uncut surfaces 60 and smooth,damage free surfaces corresponding to the cut surfaces 59. It has beenobserved that the ICP-RIE process changes the surface morphology ofinitially rough surfaces, such as the uncut surfaces 60, to dimpledsurfaces; removes damaged layers of material; and leaves initiallysmooth surfaces, such as the cut surfaces 59, unchanged.

The etched features may also be formed using known masking techniques incombination with an etching process. For example, for a SiC substrate44, the ICP-RIE process may be used or alternatively a wet chemistryetching process, such as GaP etching may be used. Once the etchedfeatures 57 are created and the masking is removed, the etching process,e.g., ICP-RIE, may be applied to the substrate in order to createdimpled surface areas in those areas of the surface covered by themasking.

The creation of etched features using masking/etching techniques may beconsidered advantageous over the bevel cutting technique for thefollowing reasons: First, they allow for the formation of a widervariety of etched-feature geometries including, not only pyramids andtruncated pyramids, but also cones and hexagonal pyramids. Second, theyallow for the formation of a denser array of etched features. Third,they create the etched features without forming a layer of damagedmaterial.

The etched features 57 enhance light extraction by providing a furthervariance to the surface to allow TIR light to escape from the LED. Theetched features 57 in combination with the dimpled surface areas providea greater degree of light extraction compared to a flat dimpledsubstrate surface, such as shown in FIG. 1.

FIG. 3 shows another embodiment of an LED package 70 according to thepresent invention also having a flip-chip mounted LED 72 comprising asubstrate 74 and an emission region 76. The LED 72 is mounted to metallayers 78 a, 78 b with contacts 80, 82 to apply a bias to the emissionregion 76. The LED 72 is also encased in a protective transparent epoxy84.

The emitting surface 86 of the LED 72 includes a plurality of etchedfeatures 88, formed by a plurality of bevel cuts 90 in a manner similarto the etched features described with respect to FIG. 2. In addition,the LED 72 includes a sidewall cut 92 around its perimeter which iscreated using an angled saw blade. The sidewall cut 92 includes twosubstrate surfaces, a vertical sidewall surface 94 and an angledsidewall surface 96. The sidewall surfaces 94, 96, like the bevel cutsurfaces 98, have layers of damaged material associated with them.

Subsequent to the creation of the etched features 80 and the sidewallcut 94, the ICP-RIE process is applied to the substrate surface 86,including the bevel cut surfaces 98, the angled sidewall surface 96 andthe uncut surfaces 100. Because the application of the ICP-RIE processis perpendicular to the uncut surfaces 100, the process does not affectthe vertical sidewall surface 94. The end result is an emitting surface86 having numerous dimpled surface areas corresponding to the uncutsurfaces 100 and smooth, damage free surfaces corresponding to the bevelcut surfaces 98 and the angled sidewall surface 96.

In an alternative configuration, a wet chemistry etching, such as GaPetching may be applied to the emitting surface 86. Unlike the ICP-RIEetching, the GaP etching affects the vertical sidewall 94 and removesthe damage layer of material associated with it. This etching, however,does not produce a dimpled surface at the uncut surfaces 100.

The etched features 80 and sidewall cut 92 enhance light extraction byproviding a further variance to the surface to allow TIR light to escapefrom the LED. The combination of etched features 80, sidewall cuts 92and dimpled surface areas provide a greater degree of light extractioncompared to a flat dimpled substrate surface, such as shown in FIGS. 1and 2.

In accordance with the invention, the previously described embodimentsof LEDs are manufactured using methods that include etching process,particularly an ICP-RIE process. Exemplary LEDs were manufactured asfollows: In general, the ICP-RIE process was applied to bare 4H and 6HSiC wafers with standard backside surface finish. The ICP-RIE processinvolved SF₆ as the etchant and used standard processing conditions forSiC etching. Wafers were placed face down on sapphire carrier wafersduring the ICP-RIE process. Other process conditions or chemistries maybe possible, including wet chemistry etching such as GaP etching, andthe invention is in no way limited to the particular conditions andchemistries described herein.

When applied to a substrate, the ICP-RIE process removes substratematerial. In addition to removing material at an average rate per unittime, the ICP-RIE etch causes specific surfaces to form a dimpledtexture on a microscopic scale. More specifically, it has been observedthat an initially roughened substrate surface, such as that whichresults from wire cutting a substrate material core to create a wafer,will form a dimpled surface when etched, as shown in FIG. 4, while aninitially smooth surface, such as that which results from saw cutting toform bevels, will remain smooth when etched, as shown in FIG. 5. Thechange in surface morphology from an initially roughened surface to adimpled surface is shown in FIGS. 6, 7 and 8. FIG. 6 is a 20 μm×20 μmscale image of an SiC wafer before ICP-RIE etching. FIG. 7 is a 100μm×100 μm scale image of a SiC wafer after ICP-RIE etching forapproximately 5 minutes. FIG. 8 is a 20 μm×20 μm scale image of a SiCwafer after ICP-RIE etching for approximately 30 minutes.

FIG. 9 shows the evolution of the SiC surface morphology with increasingetch time. From this figure it is apparent that the dimpled produced bythe ICP-RIE process increase with increased etch time. Thus, it ispossible to control the surface morphology by adjusting the etch time toobtain the desired dimple size. The thickness of SiC removed by theetching process varies as a function of time. FIG. 10 is a graph of SiCmaterial removed verses etch time. Following the etch; wafers werecharacterized using a total integrated scatter (TIS) tool. The TISsignal gauges how effectively surface roughness internally scatterslight in a wafer and is thus a proxy for LED light extraction. TIS datashown in FIG. 11 suggest an etch time of 15 to 60 minutes is optionalfor the current process conditions.

The unique, dimpled surface texture created by the ICP-RIE etch isbeneficial in several respects. First, the dimple morphology is moreconsistent and regular compared to other surface morphologies thatresult from other well known roughening processes (e.g. mechanicallapping), which may contribute to the enhanced light extractionobserved. Second, the etch process is more controllable, and less likelyto leave a damaged surface or subsurface layer than other rougheningprocesses (e.g. mechanical lapping).

Third, the ICP-RIE etch process does not require photolithography ormasking or other patterning to generate the dimple features. It isapplied to a uniform, exposed SiC surface and the dimple features formspontaneously (although, as previously indicated, the formation of adimpled surface is dependent on the specific starting surface, i.e.,roughened verses smooth). Thus, the etch process is relatively simpleand inexpensive to integrate into the LED fabrication flow. Fourth, theICP-RIE etch process is flexible in that it can be inserted at a numberof points in the LED fabrication process, including prior to epi growth.

Exemplary Process Runs:

LED with ICP-RIE

In one series of process runs, the ICP-RIE process was applied to 900μm×900 μm LEDs as the final wafer level process step. Standard LEDwafers were fabricated similar to the XB900-type LEDs manufactured byCree Inc., of Durham, N.C., except with lateral contact geometry so thatthe n-contact was on the epi-sides of the wafer (back surface remainsbare). With all else being equal, lateral geometry devices have beenpreviously been shown to perform similarly in lamps compared toconventional, vertical geometry XB900 devices. After processing, thelateral geometry LEDs were singulated as usual, including sidewallfacets, then flip-chip mounted to a Si submount with PbSn solder bumps,and then made into lamps the normal way.

In one process run (RIE#1), a 120 minute ICP-RIE process was applied toa 4H wafer. The ICP-RIE samples resulted in 23% brighter lamps comparedto the historical average for conventional XB900 devices made fromcomparable epi material. The etch process required using a full wafer soa control sample (no etch, same wafer) was not available for directcomparison.

In another process run (RIE#3), a 120 minute ICP-RIE process wasapplied. For one 4H and one 6H wafer, the ICP-RIE samples resulted in 5%and 9% brighter lamps, respectively, compared to the historical averagefor conventional XB900 devices made from comparable epi material. Theetch process required using a full wafer so control samples (no etch,same wafer) were not available for direct comparison.

LED with Bevels and ICP-RIE

In a second series of process runs, etched features were added to thesubstrate surface using bevel cuts that were made in the back surface ofan LED wafer prior to the ICP-RIE process. The bevel cuts were madeusing an angled saw blade, set such that depth of the cuts was ˜100 μmto ˜150 μm. As in the above process runs, the LEDs were XB900-likeexcept with a lateral contact geometry. FIGS. 12-18 show some examplesof bevel cuts. In FIGS. 12 and 16, the bevel cuts are arrangeddiagonally relative to the perimeter of the LED, while in FIGS. 13-15,17 and 18, the cuts are arrange perpendicularly. In FIGS. 12, 13, 14 and16, the depth of the cuts were such that the etched features createdwere truncated pyramids. In FIGS. 15 and 17, the depth of the cuts wasincreased such that the etched features created were pyramids. In FIG.18 the saw blade shape and depth of cuts were such that the etchedfeatures created were truncated pyramids with a square, uprightprojection.

Cut geometries differ than those used in the process runs are possibleand may prove superior. For example, well known masking techniques maybe used in combination with the ICP-RIE etching process, or other wellknown etching processes, such as wet chemistry etching, to form surfacecuts that result in conical or hexagonal pyramid surface features. Inaddition to providing different etched feature geometries, thesetechniques allow for the formation of more etched features per unitarea. This is so in view of the limitations imposed by the size of thesaw blade used in the above-described bevel cutting technique. Asubstrate surface characterized by a dense population of etched featureswith shallow surface cuts is beneficial in that it may provide enoughsurface area to allow for the placement of an electrical contact on thesubstrate to produce an LED with vertical contact geometry as opposed tolateral contact geometry. The shallow cut surfaces possible when usingetched cutting also result is an overall thicker substrate relative tothe substrate produced by saw cutting. The increased thickness providesa less electrically resistive substrate which increases the currentspreading of the substrate and thus the light output of the LED.

Regarding specific process runs, in one run (RIE#6), diagonal bevel cutswere applied to a 6H wafer followed by a 30 minute ICP-RIE process. Thecuts were ˜100 μm deep. The bevel+ICP-RIE sample resulted in 22%brighter lamps compared to the ICP-RIE only sample. A sample withdiagonal cuts in only one direction gave approximately half as muchimprovement.

In another process run (RIE#7), diagonal bevel cuts were applied tothree 4H wafers followed by a 60′ ICP-RIE process. The cuts were ˜100 μmdeep. For wafers #1 and #2, the bevel+ICP-RIE sample and the ICP-RIEonly sample resulted in lamps of comparable brightness. For wafer #3,the bevel+ICP-RIE sample resulted in lamps that were 10% brighter thanthe ICP-RIE only sample. The etch required full wafers at the time socontrol samples (no etch, no bevels) were not directly available.However, the bevels and ICP-RIE surface were subsequently polished off,i.e., removed, from wafer #3 and lamps were made from thebevel+ICP-RIE+polish sample and compared to standard LED wafers that hadbeen similarly polished. This allowed us to deduce that thebevel+ICP-RIE process resulted in ˜25% brighter lamps compared tostandard LEDs.

In yet another process run (RIE#9), quarter wafers were used for theICP-RIE process. Diagonal bevels ˜100 μm deep were applied to the SiCprior to etching for (a) 30 minutes and (b) 60 minutes. For a 4H wafer,the bevel+30′ ICP-RIE and bevel+60′ ICP-RIE process resulted in 10% and14% brighter lamps, respectively, compared to control samples (no etch,no bevels). For 6H wafer, the bevel+30′ ICP-RIE and bevel+60′ ICP-RIEprocess resulted in 14% and 22% brighter lamps, respectively, comparedto control samples.

In the foregoing set of process runs, additional process steps includedthe application of faceted saw cuts (‘bevels’) across the back surfaceof the substrate, followed by an ICP-RIE process that creates areashaving dimpled surface texture and removes surface damage related to thesaw cuts. These process steps are beneficial for various reasons. First,compared to existing faceting technology, which imparts angled sidewallsonly at the perimeter of the chip, the bevels produce a larger area ofangled facets on the back surface of a chip. This allows the facetingtechnology to scale with increasing chip size.

Second, it has been shown that the bevels by themselves do not reliablyresult in better light extraction (and can even make things worse). TheICP-RIE process allows the theoretical light extraction benefits ofbevels to be realized by removing the damaged surface layer resultingfrom the cutting process.

Third, compared to an alternate method for removing surface damagerelated to the bevels—wet etching of SiC—the dimpled surface textureprovided by the ICP-RIE helps scatter TIR light into the escape cones ofthe bevels. It also may be easier to manufacture in the sense that thefront side of the wafer is easier to protect from the etchant.

LED with ATON, Bevels and ICP-RIE

In a third series of process runs, the ICP-RIE process was applied afterbevel cuts and conventional sidewall (ATON) cuts were made to lateralgeometry XB900 wafers. The LED wafer was bonded to a sapphire carrierwafer during the ICP-RIE process to prevent premature breaking at thedeep sidewall cuts. Otherwise the process was similar to that describedabove. Since the ICP-RIE process occurred last, substantially all sawdamage is removed.

In one process run (RIE#10), a 4H and 6H wafer with thebevel+ATON+ICP-RIE process resulted in 21% and 22% brighter lamps thancontrol samples (same wafer, ATON only), respectively.

Although the present invention has been described in detail withreference to certain preferred configurations thereof, other versionsare possible. For example, instead of a lateral-contact geometry LEDs,the processes described above may be applied to vertical-contactgeometry LEDs. In vertical-contact geometry LEDs, care would have to betaken to protect the n-contact metal region during the ICP-RIE process.

Other etchant chemistries, including wet chemistry may be used. Forexample, GaP etching may be used as an alternative method to ICP-RIE forremoval of surface damage. The ICP-RIE process may be applied tosubstrates of various thicknesses including those used in ultra thinLEDs such as the EZ-XT LEDs manufactured by Cree, Inc. The ICP-RIEprocess may also be applied to future ‘thin chip’ LEDs, includingchip-scale package LEDs, where a highly scattering surface roughness isdesired.

The present invention may be used in all flip-chip LED products, butespecially large area LEDs. It is easiest to implement with lateralcontact geometry devices but is applicable to vertical geometry devicesas well. The ICP-RIE process may be applied to all ATON or otherwise cutsurfaces to remove saw damage. The ICP-RIE process may be applicable forother types of LED substrates (sapphire, GaP, etc.).

The invention may allow for greater flexibility in mechanical treatmentprocesses currently applied to SiC (i.e. grit size of saw, wire sawspeed, dicing saw speed) by providing a means to remove surface damage.

FIG. 19 shows another embodiment of an LED 110 according to the presentinvention that includes a conductive substrate 112 with a semiconductoremission region 114 formed on one of its surfaces. The emission region114 is similar to the emission region 18 in FIG. 1. The LED 110 includesfirst and second contacts 116, 118 that contact the oppositely dopedlayers in the emission region 114. When a bias is applied to theoppositely doped layers, through the contacts 116, 118, light isemitted. The LED 110 may be flip-chip mounted such that the substratesurface 120 opposite the emission region 114 is the primary emittingsurface of the LED.

Portions 122 of the primary emitting surface 120 include a surfacemorphology that includes a collection of geometric elements. Attributes,including element “profile” or shape, e.g., cones, pyramids,hemispheres, and element “depth,” along with the “periodicity” ofelements, i.e., spacing between like features, e.g., peaks, of adjacentelements, may be used to characterize a particular surface morphology.As explained below, in one configuration, these morphed portions 122 ofthe emitting surface 120 are formed entirely and directly in thesubstrate 112 and preferably without the use of a mask. In otherconfigurations, the morphed portions 122 are formed at least partiallywithin the substrate. In other configurations the morphed portions 122are formed in another layer of material on top of the emitting surface120 of the substrate 112.

Other portions 124 of the primary emitting surface 120, such as theportion beneath the first contact 116, are substantially smooth. Thesmooth surface provides for a large surface area of direct contactbetween the contact 116 and the substrate 112 which in turn allows forefficient transfer of current from the contact into the substrate.

With reference to FIG. 20, in a preferred embodiment, the primaryemitting surface 120 includes additional smooth surface areas 126.Conductive elements 128 are formed on these surface areas 126 and areelectrically connected to the first contact 116. These additionalconductive elements 128 form a current spreading structure that providesfor more efficient distribution of current across the surface area ofthe substrate 112. These smooth portions 124, 126 are formed by maskingthe top surface 120 of the substrate prior to creating the morphedportions 122.

With reference to FIG. 21, in an alternative configuration, moreefficient current spreading is provided by a current spreading layer 130located on the primary emitting surface 120. In one configuration, thecurrent spreading layer 130 is a layer of transparent conductingmaterial that is deposited on the primary emitting surface 120. Thetransparent conducting material may a metal, such as Pd, Ni or Au,having a thickness of between approximately 2 nm and 20 nm; atransparent conducting oxide, such as indium tin oxide, having athickness of approximately 100 nm; or a semiconductor material.

For the semiconductor material configuration, the material may be anadditional layer of heavily doped semiconductor material that isdeposited on the primary emitting surface 120. In this context, “heavilydoped” means more doped than the substrate 112. Such semiconductormaterials may include, for example, SiC, GaN and AlInGaN. The materialgenerally has the same or similar refractive index as the substrate 112and the same n-type or p-type doping as the substrate. Thus, if thesubstrate 112 is formed of n-type SiC the layer of additional material130 may be n-type SiC or AlInGaN; and if the substrate is formed ofn-type GaN, the additional material would be n-type GaN. The thicknessof the semiconductor material layer depends on the doping concentration.For example, if the doping concentration is greater than 1²⁰ cm⁻³, athickness of approximately 100 nm should be sufficient.

With reference to FIG. 22, in another configuration, the currentspreading layer 130 is part of the substrate 112 itself. In thisembodiment, a top surface region 132 of the substrate 112 is subjectedto further doping to increase its conductivity. The heavily doped, topsurface region 132 of the substrate 112 provides current spreadingwithout the need for an additional layer of material. In this context,“heavily doped” means that the top surface region 132 of the substrate112 is more heavily doped than the remaining portion of the substrate.The thickness of this more heavily doped region 132 of the substratedepends on the doping concentration. For example, if the dopingconcentration is greater than 1²⁰ cm⁻³, a thickness of approximately 100nm should be sufficient.

Returning to FIG. 19, the morphed portions 122 of the primary emittingsurface 120 may be formed using anyone of several processes, eachemploying techniques that are well known in the art. In one method, themorphed portions 122 are formed by directly etching the primary emittingsurface 120 of the substrate 112, without the use of a mask, using a dryetching process such as reactive ion etching (RIE). This process isknown to cause substrate surfaces to assume a surface morphology likethat shown in FIG. 23. Such a morphology has been referred to as a“moth-eye” surface. See Kasugai et al., Moth-Eye Light Emitting Diodes,Mater. Res. Soc. Symp. Proc. Vol. 831, 2005 Material Research Society.

With reference to FIG. 24, in another embodiment, the morphed portions122 (FIG. 19) are formed by coating the emitting surface 120 with athin, non-continuous layer 134 of material or particles. A“non-continuous layer” as used herein means a layer, which may be formedof one or more sub-layers, having top surface elements 136 that causethe layer to have a cross section of non-uniform thickness, at amicroscopic level. In one embodiment, the density of elements in thelayer 134 and the size of the elements are selected such that the topsurface of the layer has a morphology with a periodicity, profile and,depth similar to the moth-eye surface achieved through RIE etching. Thesurface morphology 138 of the non-continuous layer 134 is thentransferred at least partially to the substrate 112 by either partiallyor completely removing the non-continuous layer. “Transferred” as usedin this context means that after partial or complete removal of thenon-continuous layer 134, the substrate 112 surface has substantiallythe same surface morphology that the non-continuous layer had prior tothe removal or partial-removal process.

The non-continuous layer 134 is preferably removed using a dry etchprocess. As a cost saving measure, the dry etching process is preferablynot an RIE process, and may be, for example, involve etching with afluorine-containing gas such as nitrogen trifluoride, nitrous oxide,ammonium trifluoride, oxygen, sulfur hexafluoride, carbon tetrafluoride,or mixtures thereof. Exemplary techniques for dry etching siliconcarbide are set forth in U.S. Pat. Nos. 4,865,685 and 4,981,551 whichare incorporated entirely herein by reference. In this embodiment, thenon-continuous layer 134 is made of material or materials that etch atapproximately the same rate as the substrate 112. Such an etching rateensures that the surface morphology 138 of the non-continuous layer 134transfers at least partially to the substrate 112.

In other embodiments, the surface morphology 138 of the non-continuouslayer 134 may not match the desired surface morphology for the substrate112. For example, the depth of the elements 136 on the surface of thenon-continuous layer 134 may be larger than desired. In this case, thenon-continuous layer 134 may be made of material or materials that etchat a faster rate relative to the substrate 112. The end result is asubstrate 112 with a surface morphology having elements with less depththan the elements 136 of the non-continuous layer 134. Thecharacteristics of the surface morphology of the non-continuous layer134 and the etch rates of the non-continuous layer relative to thesubstrate 112, allow for control of the shape of the substrate surfacemorphology. Through proper selection of each, the desired substratesurface morphology may be obtained.

In one configuration, the non-continuous layer 134 is formed bydepositing a thin layer of metal, e.g., gold or aluminum, underconditions that make the layer non-continuous. For example, the metalmay be exposed to a temperature that is high enough to result indiffusion of the metal and formation of islands projecting from thesurface of the layer. Higher temperatures and longer exposure times willresult in fewer, larger islands. Thus the size, shape and density of theislands may be controlled by temperature and exposure time to create thedesired surface morphology.

In other configurations, the non-continuous layer 134 is formed by firstdepositing a uniform layer of metal and then making the uniform layernon-uniform by 1) depositing a non-continuous mask layer over theuniform layer and then etching the layer of metal to form the desiredsurface morphology; or 2) depositing nano-particles on the uniform layerusing an aerosol or other gas-phase chemical reaction and then etchingto form the desired surface morphology on the underlying uniform layer.

In another embodiment, the non-uniform layer 134 may be formed ofnano-particles. The particles may be suspended in a liquid that isevenly deposited over the substrate surface 120 by, for example, using aspinner with a rotation speed determined by the desired thickness of thelayer of particles and the properties of the liquid. Once the liquidlayer is deposited, the liquid may be evaporated at elevated or roomtemperature to remove the liquid and leave only the particles. Inanother embodiment, a layer of particles may be sprayed directly on thesubstrate surface 120. The particles may be formed of metals such asgold or aluminum, ceramics such as alumina or silicon carbide or silicaor boron nitride, carbon such as graphite or bucky balls, or organicmaterials.

In processes using a dry etch, a damaged layer of material may remain onthe morphed portions 122 of the emitting surface 120. In these cases,the material forming the damaged layer may be removed by etching themorphed portions 122 using known chemical etching processes, such as aKOH process or flowing gases such as hydrogen or hydrogen chloride.Alternatively, the damaging affects of the material forming the damagedlayer may be substantially reduced by annealing processes. In this case,the annealing process serves two functions; it activates the dopants inthe substrate and it reduces the affect of the damaged layer.

In another embodiment, the morphed portions 122 are created using wellknown grit polishing processes. In these processes, grit particles,e.g., diamond particles, abrade the light emitting surface 120 to changethe surface morphology from a generally smooth surface to a roughenedsurface. The density of particles in the grit, the size of theparticles, and the abrasive force between the particles and the surface120 are selected such that the resultant surface morphology has aperiodicity, profile and depth similar to the moth-eye surface achievedthrough the previously described RIE etching process.

With reference to FIG. 25, in another configuration, the morphedportions 122 are formed in a layer of material 132 that is deposited ontop of the emitting surface 120 of the substrate 112. Preferably, thematerial has a refractive index that is substantially the same as thesubstrate. For example, the material 140 is deposited on a SiC substrate112 may be SiC or AlInGaN; while the material deposited in a GaNsubstrate may be GaN. The material 140 also has the same n-type orp-type doping as the substrate 112. The material may be deposited usingwell known, lower temperature techniques, such as MOCVD, CVD, HVPE, MBEor sputtering. The desired surface morphology may be obtained throughcontrol of growth conditions, such as temperature. For example, a mediumdeposition temperature is more likely to produce the desired surfacemorphology as opposed to too high or too cool deposition temperatureswhich would likely result in a smooth surface. Surface morphologyformation is also dependent on the type of wide bandgap semiconductorbeing deposited. For GaN, the group V/III ratio will significantlyimpact morphology. Also, N-polar GaN is typically highly faceted grownunder typical MOCVD growth conditions.

In another embodiment, particles of the substrate 112 material or amaterial having a similar index of refraction are deposited on the topsurface 120 of the substrate. The particles are then mechanically fixedto the surface 120 through adhesion or annealing. The size, shape anddensity of the particles are selected such that the resultant surfacemorphology 122 has a periodicity, profile and depth similar to themoth-eye surface achieved through the previously described RIE etchingprocess.

It will be apparent from the foregoing that while particular forms ofthe invention have been illustrated and described, various modificationscan be made without departing from the spirit and scope of theinvention. Accordingly, it is not intended that the invention belimited, except as by the appended claims.

1. A method of fabricating a light emitting diode (LED) including a substrate having a light emitting surface, said method comprising: applying a reactive ion etch (RIE) process to at least a portion of the light emitting surface for a time duration sufficient to change the morphology of the surface.
 2. The method of claim 1 wherein the RIE process is an inductively coupled plasma reactive ion etch (ICP-RIE) process.
 3. The method of claim 1 further comprising growing a light emission region on the surface of the substrate opposite the emission surface.
 4. The method of claim 3 wherein the RIE process is applied prior to growing the light emission region.
 5. The method of claim 3 wherein the RIE process is applied after growing the light emission region.
 6. The method of claim 1 further comprising forming a plurality of etched features associated with the light emitting surface prior to applying the RIE process.
 7. The method of claim 6 wherein the etched features are formed by cutting a plurality of bevels into the light emitting surface.
 8. The method of claim 7 wherein the cutting is done using an angled saw blade.
 9. The method of claim 7 wherein the cutting is done using a masked etching technique.
 10. The method of claim 1 further comprising forming a plurality of sidewall cuts associated with the light emitting surface prior to applying the RIE process.
 11. A method of fabricating an LED including a substrate having a light emitting surface having at least one cut surface with a light absorbing damaged layer of material, said method comprising: applying a reactive ion etch (RIE) process to the cut surface for a time duration sufficient to remove at least a portion of the damaged layer of material.
 12. The method of claim 11 wherein the RIE process is an inductively coupled plasma reactive ion etch (ICP-RIE) process.
 13. A light emitting diode (LED) formed by a process comprising: growing a light emission region on a first-side surface of a substrate, the light emission region comprising a p-type layer of material, an n-type layer of material and an active layer between the p-type layer and the n-type layer; and applying a reactive ion etch (RIE) process to at least a portion of the second-side surface of the substrate opposite the first-side surface for a time duration sufficient to change the morphology of the surface.
 14. The method of claim 13 wherein the RIE process is an inductively coupled plasma reactive ion etch (ICP-RIE) process.
 15. The process of claim 13 wherein the RIE process is applied prior to growing the emission region.
 16. The process of claim 13 wherein the RIE process is applied after growing the emission region.
 17. The process of claim 13 wherein the RIE process is applied for a time period ranging from between approximately 15 and 180 minutes.
 18. The process of claim 13 further comprising cutting a plurality of bevels into the second-side surface to form a plurality of etched features having associated surface areas that form at least part of the second-side surface.
 19. The process of claim 18 wherein the cutting is performed prior to applying the RIE process.
 20. The process of claim 13 further comprising forming a plurality of sidewall cuts forming sidewall surfaces that form at least part of the second-side surface.
 21. The process of claim 20 wherein the cutting is performed prior to applying the RIE process.
 22. The process of claim 13 further comprising forming a p-contact in contact with the p-type layer of material on the first-side surface and forming an n-contact in contact with the n-type layer of material on the first-side surface.
 23. The process of claim 13 further comprising forming a p-contact in contact with the p-type layer of material on one of the first-side surface and the second-side surface and forming an n-contact in contact with the n-type layer of material on the other of the first-side surface and the second-side surface.
 24. A light emitting diode (LED) formed by a process comprising: growing a light emission region on a first-side surface of a substrate, the light emission region comprising a p-type layer of material, an n-type layer of material and an active layer between the p-type layer and the n-type layer; creating cuts in a second-side surface of the substrate opposite the first-side surface to form at least one cut surface having a light absorbing damaged layer of material; and applying a reactive ion etch (RIE) process to at least a portion of the cut surface for a time duration sufficient to remove at least a portion of the damaged layer of material.
 25. The process of claim 24 wherein the RIE etching process is an inductively coupled plasma reactive ion etch (ICP-RIE) etching process.
 26. The process of claim 24 wherein the RIE process is applied prior to growing the light emission region.
 27. The process of claim 24 wherein the RIE process is applied after growing the light emission region.
 28. A light emitting diode (LED) comprising: a substrate having a light emitting surface having an RIE etched surface with a dimpled texture; and a light emission region on a surface of the substrate, the light emission region including an active layer between first and second oppositely doped layers.
 29. The LED of claim 28 wherein the light emitting surface comprises etched features having at least one cut surface and at least one uncut surface and the dimpled texture is present only on the uncut surfaces.
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